high accuracy eprom programmable pll die for crystal oscillators cy2037 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 march 9, 2001 2.7 features benefits ? eprom-programmable die for in-package program- ming of crystal oscillators enables quick turnaround of custom oscillators lowers inventory costs through stocking of blank parts high resolution pll with 12 bit multiplier and 10 bit di- vider enables synthesis of highly accurate and stable output clock frequencies with zero or low ppm eprom-programmable capacitor tuning array with shadow register enables fine-tuning of output clock frequency by adjusting c load of the crystal twice programmable die (cy2037a and cy2037-2). enables reprogramming of programmed part, to correct errors, and control excess inventory simple 4-wire programming interface enables programming of output frequency after packaging on-chip oscillator runs from 10?30 mhz fundamental tuned crystal lowers cost of oscillator as pll can be programmed to a high frequency using a low-frequency, low-cost crystal eprom-selectable ttl or cmos duty cycle levels duty cycle centered at 1.4v or v dd /2 provides flexibility to service most ttl or cmos applications operating frequency ? 1?133 mhz at 5v ? 1?100 mhz at 3.3v ? 1?66.6 mhz at 2.7v services most pc, networking, and consumer applications sixteen selectable post-divide options, using either pll or reference oscillator output provides flexibility in output configurations and testing programmable pwr_dwn or oe pin (cy2037a and cy2037-2) frequency select (cy2037-3) enables low-power operation or output enable function enables two frequency options for meeting different industry standards, i.e., pal/ntsc. programmable asynchronous or synchronous oe and pwr_dwn modes (cy2037 and cy2037-2) provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs low jitter outputs typically ? < 100 ps (pk-pk) at 5v and f>33 mhz ? < 125 ps (pk-pk) at 3.3v and f>33 mhz suitable for most pc, consumer, and networking applications 3.3v or 5v operation lowers inventory cost as same die services both applications small die enables encapsulation in small-size, surface mount packages controlled rise and fall times and output slew rate has lower emi than oscillators
cy2037 2 functional description the cy2037 is an eprom programmable, high accuracy, pll-based die designed for the crystal oscillator market. the die attaches directly to a low-cost 10?30 mhz crystal and can be packaged into 4-pin through-hole or surface mount packag- es. the oscillator devices can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. this enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. the cy2037 contains an on-chip oscillator and an unique os- cillator tuning circuit for fine-tuning of the output frequency. the crystal c load can be selectively adjusted by programming a set of seven eprom bits. this feature can be used to compensate for crystal variations or to obtain a more accurate synthesized frequency. the cy2037 uses eprom programming with a simple 2-wire, 4-pin interface that includes v ss and v dd . clock outputs can be generated up to 133 mhz at 5v or up to 100 mhz at 3.3v. the entire configuration can be re-programmed one time al- lowing programmed inventory to be altered or reused. the cy2037 pll die has been designed for very high resolu- tion. it has a 12 bit feedback counter multiplier and a 10 bit reference counter divider. this enables the synthesis of highly accurate and stable output clock frequencies with zero or low ppm error. the clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64 and 128. the divider input can be selected as either the pll or crystal oscillator output providing a total of sixteen separate output options. for further flexibility, the ouput is selectable between ttl and cmos duty cycle levels. the cy2037a and cy2037-2 also contain flexible power man- agement controls. these parts include both pwr_dwn and oe features with integrated pull-up resistors. the pwr_dwn and oe modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output sig- nal. when pwr_dwn or oe modes are enables, clkout is pulled low by a weak pull down. the weak pull down is easily overdriven by another active clkout for applications that re- quire multiple clkouts on a single signal path. controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the cy2037 to have low jitter and accurate outputs making it suitable for most pc, networking and consumer applications die configuration cy2037 logic block diagram v dd top view v ss v dd x g pd/oe clkout v ss x g pd/oe x d configuration crystal clkout / 1, 2, 4, 8, 16, 32, 64, 128 n/c / xx [1] x d n/c oscillator 1 2 3 4 5 6 7 8 9 11 or fs or fs mux high accuracy pll eprom n/c 10 7c803xx note: 1. for customers not bonding x d or x g pad to external pins, an alternative bonding option would be shorting the xx pad to the x d pad.
cy2037 3 on the other hand, the cy2037-3 contains a frequency select function in place of the power down and output enable modes. for example, consumer products often require frequency com- patibility with different electrical standards around the world. with this frequency select feature a product that incorporates the cy2037-3 could be compatible with both ntsc for north american and pal for europe simply by changing the fs line. the twice programmable feature is also lost in the cy2037-3, because the second eprom row is now being used for the alternate frequency. eprom configuration block ta b l e 1 summarizes the features which are configurable by eprom. please refer to the ?7c8038x/7c8034x programming specification? for further details. the specifiction can be obtained from your cypress factory representative. pll output frequency the cy2037 contains a high resolution pll with 12 bit multi- plier and 10 bit divider.the output frequency of the pll is de- termined by the following formula: where p is the feedback counter value and q is the reference counter value. p and q are eprom programmable values. power management features (except cy2037-3) the cy2037 contains eprom programmable pwr_dwn and oe functions. if powerdown is selected, all active circuitry on the chip is shut down when the control pin goes low. the oscillator and pll circuits must re-lock when the part leaves powerdown mode. if output enable mode is selected, the out- put is tri-stated and weakly pulled low when the control pin goes low. in this mode the oscillator and pll circuits continue to operate, allowing a rapid return to normal operation when the control input is deasserted. in addition, the pwr_dwn and oe modes can be pro- grammed to occur synchronously or asynchronously with re- spect to the output signal. when the asynchronous setting is used, the powerdown or output disable occurs immediately (al- lowing for logic delays) irrespective of position in the clock cy- cle. however, when the synchronous setting is used, the part waits for a falling edge at the output before powerdown or out- put enable signalis initiated, thus preventing output glitches. in either asynchronous or synchronous setting, the output is al- ways enabled synchronously by waiting for the next falling edge of the output. crystal oscillator tuning circuit the cy2037 contains a unique tuning circuit to fine-tune the output frequency of the device. the tuning circuit consists of an array of eleven load capacitors on both sides of the oscilla- tor drive inverter. the capacitor load values are eprom pro- grammable and can be increased in small increments. as the capacitor load is increased the circuit is fine-tuned to a lower frequency. the capacitor load values vary from 0.17 pf to 8 pf for a 100:1 total control ratio. the tuning increments are shown in the table below. please refer to the ?7c8038x/7c8034x pro- grammimg specification? for futher details. difference between cy2037a and cy2037-2 the cy2037a contains a shadow register in addition to the eprom register. the shadow register is an exact copy of the eprom register and is the default register when the valid bit is not set. it is useful when the prototype or production envi- ronment calls for measuring and adjusting the clkout fre- quency numerous times. multiple adjustments can be per- formed with the shadow register. once the desired frequency is achieved the eprom register is permanently programmed. some production flows do not require the use of the shadow register. if this is the case, then the cy2037-2 is the device of choice. the cy2037-2 has a disabled shadow register. the cy2037-3 contains the shadow register. frequency select feature of cy2037-3 the cy2037-3 contains a frequency select function in place of the powerdown and the output enable functions. with the frequency select feature, customers can switch two different frequencies that are configured in the two eprom rows the- definition of the frequency select pin (fs) is shown in the table below. table 1. eprom adjustable features adjust frequency feedback counter value (p) reference counter value (q) output divider selection oscillator tuning (load capacitance values) duty cycle levels (ttl or cmos) power management mode (oe or pwr_dwn) power management timing (synchronous or asynchronous) f pll 2p5 + () ? q2 + () --------------------------- f ref ? = die pad summary name die pad description v dd 1,2 voltage supply v ss 8,9 ground x d 4 crystal connection. x x 3 no connect. ( for customers not bonding x d or x g pad to external pins, an alternative bonding option would be shorting this pad to xd pad.) x g 6 crystal connection. pd/oe or fs 7 cy2037a and cy2037-2 - eprom programmable power down or output enable pad. cy2037-3 - frequency select. serves as v pp in programming mode for all devices clkout 11 clock output. also serves as three-state input during programming. n/c 5,10 no connect. (do not bond to these pads)
cy2037 4 crystal oscillator tuning circuit device functionality: output frequencies symbol description condition min. max. unit fo output frequency v dd = 4.5?5.5v 1 133 mhz v dd = 3.0?3.6v 1 100 mhz v dd = 2.7?3.0v 1 66 mhz symbol description min. typ. max. unit r f feedback resistor, v dd = 4.5?5.5v feedback resistor, v dd = 2.7?3.6v 0.5 1.0 2 4 3.5 9.0 m ? m ? capacitors have 20% tolerance c g gate capacitor 13 pf c d drain capacitor 9 pf c 0 series cap 0.27 pf c 1 series cap 0.52 pf c 2 series cap 1.00 pf c 3 series cap 0.7 pf c 4 series cap 1.4 pf c 5 series cap 2.6 pf c 6 series cap 5.0 pf c 7 series cap 0.45 pf c 8 series cap 0.85 pf c 9 series cap 1.7 pf c 10 series cap 3.3 pf table 2. frequency select pin decoding for cy2037-3 fs pin output frequency 0 from eprom row 0 configuration 1 from eprom row 1 configuration cd = eprom bit t = transistor c = load capacitor cd6 c6 cd5 c5 cd4 c4 cd3 c3 cd2 c2 cd1 c1 cd0 c0 cd3 c7 cd4 c8 cd5 c9 cd6 c10 external crystal cgo cdo rf
cy2037 5 absolute maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage?0.5 to +7.0v input voltage?0.5v to v dd +0.5 storage temperature (non-condensing) ... 55 c to +150 c junction temperature ...................................?40 c to +100 c static discharge voltage ............................................ >2000v (per mil-std-883, method 3015) operating conditions parameter description min. max. unit v dd supply voltage (3.3v) supply voltage (5.0v) 2.7 4.5 3.6 5.5 v v t aj [2] operating temperature, junction ?40 +100 c c ttl max. capacitive load on outputs for ttl levels v dd = 4.5?5.5v, output frequency = 1?40 mhz v dd = 4.5?5.5v, output frequency = 40?133 mhz 50 25 pf pf c cmos max. capacitive load on outputs for cmos levels v dd = 4.5?5.5v, output frequency = 1?66.6mhz v dd = 4.5?5.5v, output frequency = 66.6?133mhz v dd = 3.0?3.6v, output frequency = 1?40 mhz v dd = 3.0?3.6v, output frequency = 40?100 mhz v dd = 2.7?3.0v, output frequency = 1?66 mhz 50 25 30 15 15 pf pf pf pf pf x ref reference frequency, input crystal. fundamental tuned crystals only. 10 30 mhz electrical characteristics over the operating range (part was characterized in a 20 pin soic package with external crystal, electrical characteristics may change with other package types) parameter description test conditions min. typ. max. unit v il low-level input voltage v dd = 4.5?5.5v v dd = 2.7?3.6v 0.8 0.2v dd v v v ih high-level input voltage v dd = 4.5?5.5v v dd = 2.7?3.6v 2.0 0.7v dd v v v ol low-level output voltage v dd = 4.5?5.5v, i ol = 16 ma v dd = 2.7?3.6v, i ol = 8 ma 0.4 0.4 v v v ohcmos high-level output voltage, cmos levels v dd = 4.5?5.5v, i oh = ?16 ma v dd = 2.7?3.6v, i oh = ?8 ma v dd ?0.4 v dd ?0.4 v v v ohttl high-level output voltage, ttl levels v dd = 4.5?5.5v, i oh = ?8 ma 2.4 v i il input low current v in = 0v 10 a i ih input high current v in = v dd 5 a i dd power supply current, unloaded v dd = 4.5?5.5v, output frequency <= 133mhz v dd = 2.7?3.6v, output frequency <= 100 mhz 45 25 ma ma i dds stand-by current v dd = 2.7-3.6v 10 50 a r up input pull-up resistor v dd = 4.5?5.5v, v in = 0v v dd = 4.5?5.5v, v in = 0.7v dd 1.1 50 3.0 100 8.0 200 m ? k ? i oe_clkout clkout pulldown current v dd =5.0 20 a note: 2. this product is sold in die form so operating conditions are specified for the die, or junction temperature
cy2037 6 output clock switching characteristics over the operating range [3] symbol description test conditions min typ max unit t 1w output duty cycle at 1.4v, v dd = 4.5?5.5v t 1w = t 1a t 1b 1?40 mhz, c l <= 50 pf 40?66 mhz, c l <= 15pf 66?125 mhz, c l <= 25pf 125?133 mhz, c l <= 15pf 45 45 40 40 55 55 60 60 % % % % t 1x output duty cycle at v dd /2, v dd = 4.5?5.5v t 1x = t 1a t 1b 1?66.6 mhz, c l <= 25pf 66.6?125 mhz, c l <= 25 pf 125?133 mhz, c l <= 15pf 45 40 40 55 60 60 % % % t 1y output duty cycle at v dd /2, v dd = 3.0?3.6 t 1y = t 1a t 1b 1?40 mhz, c l <= 30 pf 40?100 mhz, c l <= 15pf 45 40 55 60 % % t 1z output duty cycle at v dd /2, v dd = 2.7?3.0 t 1y = t 1a t 1b 1?40 mhz, c l <= 15pf 40?66.6 mhz, c l <= 10pf 40 40 60 60 % % t 2 output clock rise time between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 50 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 25 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v?5.5v, c l = 50 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 30 pf between 0.2v dd ? 0.8v dd , v dd = 2.7v?3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 3 output clock fall time between 0.8v?2.0v, v dd = 4.5v?5.5v, c l = 50 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 25 pf between 0.8 ?2.0v, v dd = 4.5v?5.5v, c l = 15 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v-5.5v, c l = 50 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v?3.6v, c l = 30 pf between 0.2v dd ? 0.8v dd , v dd = 2.7v?3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 4 start-up time out of power-down pwr_dwn or oe pin low to high [3] 1 2 ms t 5a power down delay time (synchronous setting) pwr_dwn pin low to output low (t=period of output clk) t/2 t+10 ns t 5b power down delay time (asynchronous setting) pwr_dwn pin low to output low 10 15 ns t 6 power up time from power on [3] 1 2 ms t 7a output disable time (synchronous setting) oe pin low to output hi-z (t=period of output clk) t/2 t+10 ns t 7b output disable time (asynchronous setting) oe pin low to output hi-z 10 15 ns t 8 output enable time (always synchronous enable) pwr_dwn or oe pin low to high (t=period of output clk) t 1.5t+25 ns t 9 peak-to-peak period jitter v dd = 4.5v?5.5v, fo > 33 mhz, vco > 100 mhz v dd = 2.7v?3.6v, fo > 33 mhz, vco >100 mhz v dd = 2.7v?5.5v, fo <33 mhz 100 125 250 125 200 1% of f o ps ps ps note: 3. oscillator start time cannot be guaranteed for all crystal types. this specification is for operation with at cut crystals wi th esr < 70 ohms. 4. not all parameters measured in production testing.
cy2037 7 switching waveforms notes: 5. in synchronous mode the powerdown or output 3-state is not initiated until the next falling edge of the output clock. 6. in asynchronous mode the powerdown or output 3-state occurs within 25ns irrespective of position in the ouput clock cycle. duty cycle timing (t 1w, t 1x, t 1y , t 1z ) t 1a t 1b output output rise/fall time output t 2 v dd 0v t 3 power down timing (synchronous and asynchronous modes) clkout v dd t 4 1/f t 5a v il v ih power down 0v 1/f t 5b clkout t (synchronous [5 ] ) (asynchronous [6 ] ) power up timing clkout v dd t 6 1/f v dd -10% power up 0v min 2ns
cy2037 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. ordering information [7] note: 7. the only difference between the cy2037a and the cy2037-2 is: the cy2037-2 has the shadow register disabled. the cy2037-3 repl aces the power down options with a frequency select, and contains the shadow register. switching waveforms (continued) clkout v dd output enable 0v output enable timing (synchronous and asynchronous modes) v il v ih t 7a t 8 high impedance clkout t 7b t 8 high impedance t (synchronous [4 ] ) (asynchronous [5 ] ) ordering code type operating range cy2037awaf wafer industrial CY2037-2WAF wafer industrial cy2037-3waf wafer industrial document #: 38?00679-*d die information wafer thickness 14 0.5 mils
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